What Is CoWoS? Why Does It Limit NVIDIA GPU Shipments?

CoWoS is a critical step that turns a high-end AI GPU from a “completed wafer” into a “deployable server component.” You can think of it as the high-speed foundation connecting the GPU, chiplets, and HBM. Without enough CoWoS capacity, NVIDIA may have access to enough advanced-node wafers but still be unable to integrate compute dies, HBM, substrates, and testing into final products. That is why NVIDIA GPU shipment constraints are not simply about “not enough chips,” but about advanced packaging, HBM, substrates, yield, and system delivery working together.

Key Takeaways

• CoWoS is a 2.5D advanced packaging platform that connects GPUs, chiplets, and HBM.
• The bottleneck for high-end AI GPUs has shifted from wafers alone to packaging and memory.
• Blackwell depends more heavily on CoWoS-L than Hopper did on CoWoS-S.
• A CoWoS shortage can prevent qualified GPU dies from becoming finished accelerator products.
• Capacity expansion is underway, but yield, HBM supply, and customer competition still constrain delivery.
• To track NVIDIA shipments, you need to watch TSMC, HBM suppliers, and the server supply chain together.

What Is CoWoS: The High-Speed Base Between GPUs and HBM

CoWoS stands for Chip on Wafer on Substrate. It is essentially TSMC’s advanced packaging platform for high-performance computing. It does not solve the question of “how to manufacture transistors,” but rather “how to connect multiple high-performance dies, HBM, and packaging substrates at high speed.” For AI GPUs, the value of CoWoS lies in placing compute chips and high-bandwidth memory extremely close to one another, improving bandwidth, reducing power consumption, and supporting larger system-level chip designs.

Traditional packaging is more like placing a single chip into a package and connecting it to external memory and other components through a circuit board. AI GPUs face a more complex challenge: model training and inference require large volumes of data to move rapidly between the GPU and memory, and ordinary PCB traces struggle to meet the required bandwidth and latency. CoWoS exists to place GPU dies, logic chiplets, and HBM stacks onto a high-density interconnect platform.

You can think of CoWoS as a “high-speed chip campus.” The GPU is the compute core, HBM is the high-bandwidth warehouse right next to it, and the interposer or redistribution layer is the campus highway system. The wider the roads and the shorter the distance, the faster data moves and the lower the energy cost.

TSMC’s CoWoS is not a single process, but a family of technologies. CoWoS-S uses a large silicon interposer and is suited to ultra-high-performance computing applications. CoWoS-R uses an RDL interposer and offers more structural flexibility. CoWoS-L combines RDL with local silicon interconnects, making it suitable for larger and more complex HPC products. TSMC discloses that CoWoS-S can support interposers up to about 3.3 times reticle size, while larger designs are better suited to CoWoS-L or CoWoS-R.

This is also where many misunderstand CoWoS. CoWoS is not simply a “chip package shell.” It is a system-level engineering platform that determines whether GPUs and HBM can work together at high speed. The larger the AI chip, the more HBM it uses, and the more complex the chiplet structure becomes, the closer packaging gets to the core technology itself. When analyzing NVIDIA, TSMC, advanced packaging equipment makers, or HBM suppliers, you should not only ask “who can manufacture advanced-node wafers,” but also “who can reliably deliver large-area, high-yield, high-bandwidth system-level packaging.”

Summary: The core value of CoWoS is integrating compute dies, HBM, and other chiplets into one high-density interconnect platform. It gives AI GPUs higher memory bandwidth, lower data-movement power consumption, and stronger system scalability. Understanding CoWoS is essential to understanding why advanced packaging has evolved from a back-end semiconductor process into a strategic bottleneck in the AI chip supply chain.

Why High-End AI GPUs Increasingly Depend on CoWoS

High-end AI GPUs use CoWoS not to make the chips look more compact, but to scale compute, memory, and interconnect at the same time. Large model training and inference are not only about the number of compute cores; they also require constant movement of parameters, activations, and cached data into compute units. If memory bandwidth cannot keep up, the GPU may have plenty of compute power but not enough data to fully use it. CoWoS is designed to relieve this bottleneck.

AI chips used to be understood mainly as an “advanced-node race”: whoever used a more advanced node would gain stronger transistor density and energy efficiency. In the large model era, another issue has become more important: the cost of data movement. The larger the model, the more frequently data must move between GPU and memory, and interconnect distance, bandwidth, and power consumption all affect real-world performance.

H200 emphasizes HBM3E because generative AI and HPC workloads increasingly require larger memory capacity and faster memory bandwidth. With Blackwell, packaging requirements rise even further. The NVIDIA Blackwell architecture shows that a Blackwell GPU consists of two near-reticle-limit dies connected as a unified GPU through a 10 TB/s chip-to-chip interconnect. The NVIDIA Blackwell platform also emphasizes that Blackwell targets trillion-parameter model training and real-time inference, requiring stronger chip-to-chip communication and system-level interconnect.

This means chiplet architecture has not reduced the importance of advanced packaging. Instead, it has shifted the system challenge from “can one large chip be manufactured” to “can multiple chips be combined reliably and at high speed.”

Consumer GPUs can use relatively traditional packaging and GDDR memory, but data center AI GPUs require extremely high bandwidth, high parallelism, and strong reliability. HBM itself is stacked memory, but it still needs to connect to the GPU through an interposer with a very wide interface. Without 2.5D packaging platforms like CoWoS, the data channel between GPU and HBM would struggle to reach the bandwidth density needed for high-end AI training.

For investors and supply-chain observers, this means NVIDIA’s competitiveness does not only come from CUDA, GPU architecture, and system software. It also depends on whether NVIDIA can secure enough advanced packaging, HBM, and server system resources. When tracking NVDA, TSM, AMD, AVGO, MU, and other related companies through U.S. stock information, their data center revenue, gross margin, and guidance should be assessed together with packaging capacity, memory supply, and delivery lead times.

Summary: High-end AI GPUs depend on CoWoS because the core bottlenecks of AI computing increasingly come from memory bandwidth and chip-to-chip interconnect. Even if the GPU die is powerful, system performance will still be limited if it cannot exchange data with HBM at high speed. CoWoS enables the GPU, HBM, and chiplets to form a high-bandwidth system at the package level, making it a critical infrastructure layer for Blackwell and future AI GPUs.

Why CoWoS Limits NVIDIA GPU Shipments

CoWoS limits NVIDIA GPU shipments because a GPU die cannot be sold directly to cloud providers or server customers after wafer manufacturing is complete. It must be integrated with HBM, package substrates, power structures, and thermal designs, then pass final testing before becoming a deployable AI accelerator. If CoWoS capacity, HBM, or testing capacity is insufficient, qualified dies can get stuck in the middle of the production flow.

A high-end AI GPU typically goes through the following steps before delivery:

1. TSMC completes advanced-node wafer manufacturing.
2. The wafer is diced and qualified GPU compute dies are selected.
3. HBM suppliers complete memory stacking, testing, and customer qualification.
4. GPUs, HBM, and chiplets enter CoWoS integration.
5. The package is connected to a large substrate to form a complete package.
6. Power delivery, thermal management, signal integrity, and reliability tests are completed.
7. The product enters accelerator card, server motherboard, or full-system assembly.
8. Cloud providers and enterprise customers complete deployment and acceptance.

The key point is that every step must match. If GPU dies are sufficient but HBM is not, packaging cannot be completed. If HBM is sufficient but CoWoS-L capacity is short, the chip still cannot ship. If packaging is completed but test yield is unstable, actual shipments will remain lower than input volume.

Epoch AI’s estimate of the AI chip supply chain indicates that in 2025, NVIDIA, Google, AMD, and Amazon together consumed more than 90% of global CoWoS packaging capacity and HBM supply, while NVIDIA alone accounted for about 60% of CoWoS supply. These figures are research estimates rather than company-disclosed numbers, but they illustrate the reality that advanced packaging and HBM can become short-term bottlenecks more easily than advanced logic wafers.

TSMC has been expanding capacity. The TSMC Q1 2025 earnings call mentioned that the company was working to double CoWoS capacity in 2025 to support customer demand. But doubling capacity does not mean shipments immediately double, because new equipment installation, material introduction, customer qualification, and yield ramp all take time. The TSMC Q1 2026 earnings call still showed tight advanced packaging supply, with TSMC also needing to work with OSAT partners to expand back-end capacity.

If you view the AI GPU supply chain as a production line, CoWoS is like the narrowest high-speed gate in the middle. Even if wafer production is fast and server demand is strong, final GPU delivery will remain constrained if this gate cannot process enough large packages.

Summary: CoWoS limits NVIDIA GPU shipments not because it is merely a “packaging step,” but because high-end GPUs must complete system integration of GPU, HBM, substrate, and testing at the packaging stage. If any link among CoWoS, HBM, yield, and server assembly is tight, NVIDIA’s nominal demand cannot fully turn into actual deliveries.

From Hopper to Blackwell: Why the Bottleneck Is Shifting from CoWoS-S to CoWoS-L

NVIDIA’s demand for advanced packaging has not fallen as Hopper matures. Instead, with Blackwell, it has shifted toward the more complex CoWoS-L. Hopper mainly depends on CoWoS-S, while Blackwell requires larger and more complex multi-chip packaging. In other words, the issue is not “NVIDIA is using less CoWoS,” but “the type of CoWoS NVIDIA needs is changing,” and old capacity and new capacity are not perfectly interchangeable.

Jensen Huang’s comments on changing packaging needs are important: Blackwell will use a large amount of CoWoS-L, while Hopper continues to use CoWoS-S. NVIDIA is not reducing its need for advanced packaging; it is shifting that demand toward CoWoS-L. The same Reuters report also noted that Blackwell chip sales were constrained by TSMC’s manufacturing capacity, with packaging remaining one of the bottlenecks.

Why is CoWoS-L harder? Because it is not simply a larger version of CoWoS-S. Large packages bring higher routing density, more complex thermal expansion stress, stricter flatness control, and more demanding testing. The larger the package area, the higher the loss caused by any local defect. The more chiplets and HBM stacks there are, the more system-level yield depends on all components being qualified at the same time.

This is why advanced packaging expansion is slower than many market participants expect. Building factories and buying equipment are only the first steps. Material matching, process tuning, customer qualification, and production yield ramp must follow. TrendForce’s assessment of 2.5D packaging shortages noted that AI computing chips are consuming more wafer and packaging resources per unit, and that the severe global shortage of 2.5D packaging may only begin to ease slightly in 2027.

This has two implications for NVIDIA and TSMC. First, continuing Hopper production consumes CoWoS-S, while Blackwell volume ramp requires CoWoS-L, so capacity mix adjustment is itself a challenge. Second, product upgrades increase per-GPU consumption of package area, HBM, and testing resources. Even if TSMC increases total capacity, resource consumption per unit may rise at the same time.

When trading or researching NVDA, TSM, AMD, SK hynix, Micron, and other supply-chain names, you should not only look at whether the next-generation GPU has been released. You also need to ask whether the corresponding packaging route is mature, whether HBM has been qualified, and whether suppliers can support stable mass production.

Summary: From Hopper to Blackwell, the CoWoS bottleneck has not disappeared. It is shifting from the more mature CoWoS-S toward the more complex CoWoS-L. Blackwell’s dual-die design, larger package area, and higher HBM demand increase the amount of advanced packaging resources consumed per unit. If capacity expansion cannot match the changing product mix, NVIDIA GPU delivery can still be constrained.

When Will the CoWoS Bottleneck Ease? Signals to Watch

CoWoS supply is improving, but it is unlikely to become fully unconstrained in a single quarter. A more reasonable view is that capacity will expand gradually and the shortage will narrow over time, but bottlenecks may migrate between CoWoS-L, HBM, package substrates, test yield, and full server systems. You should watch not only TSMC’s capacity announcements, but also effective capacity, customer allocation, yield, and end-market delivery cycles.

TrendForce’s estimate of the CoWoS supply-demand gap suggests that as TSMC and partners expand capacity, the CoWoS gap may narrow from around 20% to around 10% by the end of 2026. The report also mentioned that TSMC’s monthly CoWoS capacity in 2026 may reach 120,000 to 140,000 wafers, with OSAT partners adding further supply. These figures are supply-chain estimates and should not be treated as formal TSMC shipment commitments.

More recent expansion signals are also worth watching. Reuters’ report on two new advanced packaging plants in Chiayi Science Park shows that TSMC is still investing around advanced packaging. The issue is that new facilities usually require a clear time lag from construction, equipment move-in, and trial production to stable mass production.

In the medium term, the CoWoS bottleneck may ease, but the continued upgrade of AI chip platforms could create new constraints. After Blackwell, HBM4, larger packages, optical interconnects, liquid cooling, power delivery, and rack-scale systems may all become new short boards. The supply chain is like a set of changing barrel staves: once CoWoS becomes less constrained, HBM, advanced-node capacity, substrates, or full-system delivery may become the next shortest stave.

When turning supply-chain analysis into trading observation, transaction cost also matters. AI chip-related stocks are volatile, and supply-chain information changes quickly. Before placing an order, in addition to studying the capacity and earnings of NVDA, TSM, AMD, MU, and other companies, you also need to confirm order types, execution prices, platform fees, and external agency fees. For example, Biya supports multi-asset trading across U.S. stocks, Hong Kong stocks, and digital assets. Its U.S. stock trading fees state that U.S. stock trading commission is USD 0, while platform fees, external agency fees, and other charges are subject to the fee schedule and order page display. Service availability depends on the user’s location, identity verification result, platform rules, and applicable laws and regulations; public market information and fee structures do not constitute investment advice.

Summary: The CoWoS bottleneck is moving from “absolute shortage” toward an “expansion catch-up” phase, but the supply chain will not become broadly unconstrained simply because one capacity metric improves. You should monitor CoWoS-L effective capacity, HBM qualification, packaging yield, OSAT collaboration, server delivery, and cloud CAPEX together. For NVIDIA, GPU shipments are not determined by one capacity number, but by the full-chain match from wafers, HBM, and packaging to final system delivery.

If you follow the AI chip supply chain, CoWoS is a central lens for understanding NVIDIA, TSMC, HBM suppliers, and advanced packaging equipment makers. In the short term, it affects GPU delivery schedules and cloud procurement cycles. In the medium term, it influences TSMC capital expenditure, equipment orders, HBM allocation, and AI server shipments. In the long term, it shows that AI computing is moving from “single-chip performance competition” toward “system-level manufacturing capability competition.” When using a multi-asset trading tool such as Biya to track related companies, it is better to evaluate share prices, earnings, capacity, fee structures, and personal risk tolerance in one framework rather than making decisions based on a single headline.

FAQ

Do All NVIDIA GPUs Need CoWoS?

No, not all NVIDIA GPUs need CoWoS. CoWoS is mainly used for high-end data center AI GPUs such as H100, H200, and Blackwell. Consumer GeForce GPUs or certain lower-spec products may use different packaging and memory solutions. The key is to distinguish data center AI accelerators from ordinary graphics cards.

Will NVIDIA GPU Output Rise Immediately After CoWoS Capacity Doubles?

No, GPU output will not rise immediately in line with CoWoS capacity. Capacity expansion still requires equipment installation, process tuning, customer qualification, yield ramp, HBM matching, and server assembly. Higher nominal capacity usually improves supply flexibility first, then gradually shows up in NVIDIA GPU delivery cycles.

What Is the Difference Between a CoWoS Shortage and an HBM Shortage?

CoWoS is the advanced packaging capability that integrates GPUs, HBM, and chiplets, while HBM is the high-bandwidth memory integrated into the package. If either one is insufficient, high-end AI GPU shipments can be affected. CoWoS is more of a manufacturing integration bottleneck; HBM is more of a memory supply and qualification bottleneck.

Can Samsung or Intel Packaging Replace TSMC CoWoS?

A full short-term replacement is difficult. Samsung and Intel both have advanced packaging routes, but NVIDIA’s high-end GPU designs, wafer manufacturing, HBM qualification, and packaging yield have long been built around the TSMC ecosystem. Substitution is not only about technical feasibility; it also involves redesign, qualification cycles, and mass production stability.

Do AMD and Cloud Self-Developed Chips Compete for CoWoS Capacity?

Yes, they create capacity competition. AI accelerators such as AMD Instinct, Google TPU, and Amazon Trainium also require advanced packaging and HBM resources. NVIDIA remains one of the largest demand sources, but CoWoS allocation depends on customer contracts, product roadmaps, packaging type, and mass-production priority.

How Should Investors Track the Impact of CoWoS on NVDA Stock?

Investors should watch NVIDIA data center revenue, Blackwell delivery pace, TSMC advanced packaging expansion, HBM supplier capacity, and cloud provider CAPEX together. Better CoWoS supply may support shipment growth, but it does not guarantee share-price gains. Valuation, market expectations, and risk appetite also matter.